The present invention finds application in connection with thin silicon plates or wafers formed to support a multiplicity of monolithically integrated data processor circuits. More particularly, the invention is for the production of junction field effect transistor (JFET) integrated circuit elements formed on silicon wafers and used to interface devices such as infrared detector elements to a processing network that amplifies, stores and interprets detected infrared frequency signals.
The infrared spectrum covers a range of wavelengths longer than the visible wavelengths, but shorter than microwave wavelengths. Visible wavelengths are generally regarded as between 0.4 and 0.75 micrometers. The infrared wavelengths extend from 0.75 micrometers to 1 millimeter. The function of infrared detectors is to respond to the energy of a wavelength within some particular portion of the infrared region.
Heated objects generate radiant energy having characteristic wavelengths within the infrared spectrum. Many current infrared image detection systems incorporate arrays with large numbers of discrete, highly sensitive detector elements, the electrical outputs of which are connected to processing circuitry. By analyzing the pattern and sequence of detector element excitation, the processing circuitry can identify and track sources of infrared radiation. Though the theoretical performance of such contemporary systems is satisfactory for many applications, it is difficult to construct structures that adequately interface large numbers of detector elements with associated circuitry in a practical and reliable manner. Consequently, practical applications for contemporary infrared image detector systems have necessitated further advances in the areas of miniaturization of the detector array and accompanying circuitry, of minimization of circuit generated noise that results in lower sensitivity of the detected signal, and of improvements in the reliability and economical production of detector arrays and the accompanying circuitry.
Contemporary arrays of detectors, useful for some applications, may be sized to include 256 detector elements on a side, or a total of 65,536 detectors, the size of each square detector being approximately 0.009 centimeters on a side, with 0.00116 centimeters spacing between detectors. Such a subarray would therefore be 2.601 centimeters on a side. Interconnection of such a subarray to processing circuitry would require connecting each of the 65,536 detectors to processing circuitry within a square, a little more than one inch on a side. Each subarray may, in turn, be joined to other subarrays to form an array that connects to 25,000,000 detectors or more. As would be expected considerable difficulties are presented in electrically connecting the detector elements to associated circuitry, and laying out the circuitry in a minimal area. The problems of forming processing circuitry in such a dense environment require minimization of the surface area used for the circuitry.
The outputs of the detector elements typically undergo a series of processing steps in order to permit derivation of the informational content of the detector output signal. The more fundamental processing steps, such as preamplification, tuned band pass filtering, clutter and background rejection, multiplexing and fixed noise pattern suppression, are preferably done at a location adjacent the detector array focal plane. As a consequence of such on-focal plane, or up-front signal processing, reductions in size, power and cost of the main processor may be achieved. Moreover, on-focal plane signal processing helps alleviate performance, reliability and economic problems associated with the construction of millions of closely spaced conductors connecting each detector element to the signal processing network.
Aside from the aforementioned physical limitations on the size of the detector module, limitations on the performance of contemporary detection systems can arise due to the presence of electronic circuit generated noise, in particular, from the preamplifier. Such noise components can degrade the minimal level of detectivity available from the detector.
A type of noise that is particularly significant where the preamplifier operates at low frequency is commonly called flicker or 1/f noise. Because 1/f noise can be the principal noise component at low frequencies of operation, it is highly desirable that circuits operating within such frequencies be constructed in such a manner as to decrease 1/f noise to an acceptably low level.
U.S. Pat. No. 4,633,086, to Parrish, Input Circuit For Infrared Detector, assigned to the common assignee, describes one technique for biasing the on-focal-plane processing circuit to maintain the associated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal to noise ratio of the circuit.
Reduction of 1/f noise in the preamplifier, where the preamplifier transistor is a field effect device, is conventionally obtained by increasing the area of the channel region under the gate. This large area over the semiconductor substrate surface results in a decrease in circuit component density or decreased circuit component miniaturization. In the present invention, the channel region of a junction field effect transistor (JFET) is formed in a trench in the semiconductor. The transistor then occupies far less semiconductor substrate surface and so enables a high component density circuit to be obtained.
In co-pending applications, Ser. No. 07/664,464, filed on Mar. 1, 1991, entitled TRENCH GATE COMPLIMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR; Ser. No. 07/664,459, filed on Mar. 1, 1991, entitled TRENCH GATE METAL OXIDE SEMICONDUCTOR TRANSISTOR; and Ser. No. 07/683,509, filed on Apr. 8, 1991, entitled METHOD OF MAKING TRENCH MOSFET CAPACITOR CELL FOR ANALOG SIGNAL PROCESSING, all presently pending, applicant has disclosed constructions of a trench gate MOS field effect transistor (MOSFET) alone and integrated with a capacitor in a single trench. Such constructions provide large area trench gate regions to obtain low 1/f noise without consuming large amounts of semiconductor surface area. The present invention expands on the disclosure of applicants co-pending applications by modifying the transistor construction to provide additional radiation hardness to the circuit. Conventional construction of a MOSFET utilizes a layer of silicon dioxide separating the gate electrode from the channel semiconductor region. When such a transistor it is irradiated by gamma rays; one result is to establish a residual charge in the silicon dioxide, which provides a constant bias on the transistor channels. This bias typically impedes the operation of the transistor by, for example, keeping the transistor in an on state, or by varying its threshold.
Radiation hardness is provided by a different transistor construction wherein an insulating layer in the gate region is eliminated. The junction field effect transistor (JFET) is characterized by a construction wherein the insulating layer is replaced by a p-n junction which does not accumulate a bias charge on irradiation. Consequently, the JFET construction avoids the need to use materials that would result in storing a residual charge upon irradiation. It further extensively utilizes silicon nitride as a dielectric and insulator in place of silicon dioxide. Since silicon nitride does not accumulate charge from ionizing radiation, it avoids spurious residual charge effects that can otherwise appear at silicon dioxide, silicon interfaces.